A considerable amount of effort has gone into the development of gallium arsenide as an alternative semiconductor material for high-speed digital computers, because of its known advantage in gate switching speed over silicon-based integrated circuits. However, despite this switching speed advantage, gallium arsenide has not achieved widespread use. Although there are many reasons for the less than rapid acceptance of gallium arsenide in the semiconductor industry, one reason of particular importance in the field of large high-speed digital computers, or supercomputers, is the lack of effective systems for implementing custom or semi-custom gallium arsenide-based integrated circuits which are needed because of custom design requirements for various sections within the architecture of the computer system. Off-the-shelf small-scale integration of gallium arsenide is available in the prior art and can be used for implementing custom designs of supercomputers. However, the relatively small number of logic gates per package limits the overall performance of the computer due to propagation delays between packages. Hence, any speed improvement in gate switching speed over silicon is at least partially lost in the interpackage propagation delays. In the meantime, silicon-based integrated circuit technology has continued to evolve and has provided increased performance through improvements in packaging density and large-scale integration techniques. Attempts to translate the circuit designs and integration techniques which have been successful in silicon into the field of gallium arsenide has not been successful in application to the design of large computing systems.
Therefore, there exists a need in the high-speed computer industry for a simple and effective design system for implementing custom or semi-custom gallium arsenide-based integrated circuits. Due to the unique characteristcs of gallium arsenide semiconducting materials and the differences between these materials and silicon, unique constraints and requirements are placed on a gallium arsenide-based logic system heretofore unknown in the prior art. Such a logic design system should allow the fabrication of integrated circuits with packaging densities of equivalent gates per chip at a much higher level than currently available in the prior art. Such a logic design system should also be simple and easy to maintain by having a minimum number of cell types to choose from, keeping the number of fabrication steps and cell masks required for implementation at a minimum.